Open Access Open Access  Restricted Access Subscription or Fee Access

Optimization of a Digital Adder Design Using MOSFET and FinFET Technology

Ritu Dagar, Preet Kaur

Abstract


Abstract

In this study, a very low power high speed Adder is presented by using short gate mode technique and voltage scaling system for FinFET. MOSFET and FinFET technique is used on 32 nm by adders which compare delay and average power. Parametric study of fins vs. power is also performed in the study. Synopsys HSPICE software is used for obtaining the simulation results. Simulation results show that low power is obtained in short gate mode Adder technique. When FinFET is applied in the Adder, delay is also improved.

Keywords: 32 nm, FinFET, adder, MOSFET, CMOS

Cite this Article

Ritu Dagar, Preet Kaur. Optimization of a Digital Adder Design Using MOSFET and FinFET Technology. Journal of Electronic Design Technology. 2018; 9(2): 30–33p.



Full Text:

PDF

Refbacks

  • There are currently no refbacks.


Copyright (c) 2018 Journal of Electronic Design Technology