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Implementation of Weighted Round Robin Algorithm in Shared Bus Architectures

Tejas U. Patel, Devendra Patle

Abstract


Abstract
The application domain of System-On-Chips (SoC) includes mobile devices, end terminals, multimedia terminals, automotive, set-top-boxes, games, processors etc. The SoC design paradigm relies heavily on reuse of intellectual property cores, enabling designers to focus on functionality and performance of the overall system. This is possible if IP cores are equipped with highly optimized interface for plug and play insertion into communication architecture. To this purpose the virtual Socket Interface Alliance represents an attempt to set the characteristics of industry wide, thus facilitating the match of pre-designed software and hardware blocks from multiple sources. The SoC interconnect must be designed and optimized to support a heterogeneous mix of data paths which may inherently have widely varying performance characteristics. The fabric must reliably deliver the required throughput and hide latency for performance critical paths while simultaneously managing the flow of traffic for slower paths and ports requiring lower bandwidth. Thus the system bus as a whole must strike the appropriate between latency and throughput for the collection data paths. Optimizing around this balance is essential to minimizing power, performance, area (PPA) costs and avoiding an inefficient, over-designed SoC.


Keywords: SoC, multiprocessor, arbiter, interconnect, arbitration

Cite this Article
Tejas Patel, Devendra Patle. Implementation of Weighted Round Robin Algorithm in Shared Bus Architectures. Journal of Electronic Design and Technology. 2017; 8(2): 34–40p.


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