Stability Analysis in SRAM Cell for Deep Submicron Design

Abstract

Abstract

Memory is an integral part of present day battery operated and hand held electronic gadgets. As the size of devices shrinks so does the size of memory used in these devices also, this increases the demand for low power devices. Leakage current is one of the prominent factors that contribute to significant portion of the total power dissipation; in fact at lower technologies it becomes comparable to switching component. Device scaling also affects various electrical parameters like noise voltage and cell stability. The static noise margin (SNM) of cell greatly determines its stability. To address upon this issue various techniques have been proposed at various levels of design cycle. This paper analyzes SNM for 6T SRAM cell with respect to various parameters like cell ratio (CR), pull-up ratio (PR), supply voltage (V_dd), data retention voltage (DRV) and temperature. It also analyzes the variation of read static noise margin (RSNM) and writes static noise margin (WSNM) with the variation in V_dd. simulations are carried out using cadence virtuoso tool in 90 nm and 45 nm technology.

Keywords: SRAM, Static Noise Margin, DRV, CR, PR, RSNM, WSNM

Cite this Article

Tripti Tripathi, D.S. Chauhan, S.K. Singh. Stability Analysis in SRAM Cell for Deep Submicron Design. Journal of Electronic Design Technology. 2018; 9(2): 1–6p.