Performance Analysis of Complimentary Pass Transistor Logic Based Multiplexer Using Dual-gate FinFET Technology

Abstract

Abstract

This paper presents the design and analysis of double gate FinFET complimentary pass transistor logic (CPL) multiplexer. The circuit of multiplexer (MUX) using CPL is used for comparison of performance parameters like average power consumption, rise/fall time, delay, slew rate, PDP and EDP. Multiplexer is a digital circuit, it has inputs and select line; select lines are used for select input lines to transfer data to the output end. The multiplexer are used to select particular input within many inputs and used to transfer information in decided time. In this paper, a CPL DG-FinFET technique is used to analyze performance parameters of multiplexer circuit. The conventional CMOS circuit and DG-FinFET circuit parameters are compared, as results indicate the performance increased of the DG-FinFET based CPL multiplexer circuit compare to CMOS. In proposed work, multiplexer use supply voltage of 0.9V. The design and simulation of DG-FinFET based complimentary pass transistor logic multiplexer is done by using 32 nm technology at HSPICE Tool. All the parameters average power, delay, rise time fall time, slew rate, PDP, EDP of 2-to-1 DG-FinFET based MUX improved 26%, 2%, .5%, 63%, 73.52%, 27% and 31%, respectively. For 4-to-1 DG-FinFET based MUX improved 66.45%, .481%, 40.54%, 68%, 77.67%, 66.56% and 66.76%, respectively and for 8-to-1 DG-FinFET based MUX improved 79.25%, 2.46%, 1%, 72.76%, 73.45%, 79.78% and 80.29%, respectively.

Keywords: MUX, power, delay, FinFET, Slew rate, PDP, FinFET, CPL, HSPICE

Cite this Article

Saurabh Kumawat, Purushottam Kumawat, Suchitra. Performance Analysis of Complimentary Pass Transistor Logic Based Multiplexer Using Dual-gate FinFET Technology. Journal of Microelectronics and Solid State Devices. 2018; 5(1): 41–48p.