Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology

Abstract

Abstract
In this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and FinFET transistor model a (PTM) BSIM-CMG model have been used respectively by using 0.9 V power supply and simulations are done using HSPICE at 32 nm technology. The performance parameters were measured and compared are average power, maximum current, power delay product, rise/fall time, slew rate, delay, average current and energy delay product. It is observed that reduction in the average power and delay is 56.20%, 25.30% and EDP and PDP of CMOS to FinFET is achieved by 67.28%, 62.72% respectively. Rise time, fall time and slew rate are reduced 63.46%, 69.72% and 49.99% and maximum current and average current are low by 24.09% and 45.81%.

Keywords: 1-bit Full Adder, CMOS, average power, PDP, maximum current, EDP, slew rate, DG-FinFET, HSPICE

Cite this Article
Saurabh Kumawat, Purushottam Kumawat, Akanksha Choudhary. Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology. Journal of Microelectronics and Solid State Devices. 2017; 4(3): 1–8p