High Throughput LMS Adaptive Filter Architectures using Pipelining and Parallel Processing

Abstract

Abstract

In this paper, a study on existing designs of adaptive filter based on LMS algorithm is done. The primary aim is to reduce the critical path delay and thereby improve throughput. The excess use of multipliers or the lack of a time efficient one and longer cycle periods reduces the effectiveness of any adaptive filter implementation. Here, a simple and highly time efficient Vedic multiplier is used in the implementation of filter. Pipelining is employed to LMS adaptive filter to reduce critical path and L fold parallelism is employed using BLMS to increase the throughput. The main drawbacks of both, the former being an increase in latency and the latter being an increase in hardware make the former more suitable for lower filter order and the latter for higher order implementation. The structures were simulated in Xilinx and the performance parameters observed in Cadence. Suitable conclusion was drawn among pipeline and parallel techniques using filter implementations for different tap size i.e., 7, 12 and 32.

Keywords: LMS adaptive filters, Vedic multiplier, BLMS, DLMS

Cite this Article

Anjaneya B. Anirudh, Pramod P. High Throughput LMS Adaptive Filter Architectures using Pipelining and Parallel Processing. Journal of Microelectronics and Solid State Devices. 2018; 5(2):      11–19p.