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A Novel Design for High Speed & Area Efficient Compressor Based Vedic Multiplier

Aji Harikumar, Reneesh C. Zacharia

Abstract


Multipliers are the most important part in any arithmetic and logic unit, 

Abstract

Multipliers are the most important part in any arithmetic and logic unit, accumulators and digital signal processors. Due to the increasing constraints on delay, the design of faster multipliers is emphasized. Among several multipliers, Vedic multipliers are preferred for their speed of operation. Here the proposed Vedic multiplication techniques are based on “URDHVA TIRYAKBHYAM” a fast and efficient technique. The Aim of this project is to develop a multiplier using modified Adder which implements the "URDHVA TIRYAKBHYAM" sutra with improved speed of operation. Adders are vastly implemented in the critical path of many blocks of microprocessor chips. The efficiency of the digital system is greatly influenced by the performance of these adders. In this paper, new innovative compressor adders are proposed. When different multiplier circuits are used then it is observed that compressor based multipliers are more efficient than others. The most important parameters to be noted to measure the performance of adder designs are computation time and area. To compare results we have simulated different types of adders in existing logic by using Cadence Virtuoso tool and Xilinx 14.7.

Keywords: Vedic multipliers, Urdhva Tiryakbhayam sutra, Compressor adders

Cite this Article

Aji Harikumar, Reneesh C. Zacharia. A Novel Design for High Speed & Area Efficient Compressor Based Vedic Multiplier. Journal of Microelectronics and Solid State Devices. 2018; 5(3):1–10p.



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