Ultra Low-Power 9-Transistor Flip-Flop Design

Abstract

Abstract

The use of very large scale integration technology in high performance computing, wireless communication, consumer electronics has been rising at a very fast rate.  The challenge for VLSI technology is mainly in leakage power consumption. Flip-Flops (FFs) are the basic storage elements used extensively in digital system designs. It accounts for 20%–45% of the total system power and may considerably impact the chip area. In this paper, an ultra-low-power true single-phase clocking (TSPC) flip-flop design, a modification of logic structure reduction flip flop (LRFF) design achieved using only 9-transistors is addressed. The performance levels of eight FF designs were compared. A TSMC 90 nm CMOS process was selected as the implementation technology. The analysis and the comparison was done using Tanner EDA tool.

Keywords: True single-phase clocking, Logic structure reduction FF, Complementary pass-transistor logic

Cite this Article

Chithra M, Suresh Kumar E, Ajith KB. Ultra Low-Power 9-Transistor Flip-Flop Design. Journal of Microelectronics and Solid State Devices. 2018; 5(3): 27–32p.