Performance Analysis of 1-Bit Half Adder using Different Combinational MOS Logics

Abstract

 Abstract

Adder is required for many processors designing like microprocessors, digital signal processors, image processing and various VLSI applications. The overall performance of system depends upon the adder circuits due to its presence mainly in critical paths of system. This paper presents half adder circuits using different combinational MOS logics. All the circuits were analyzed to find the most suitable circuit which consumes less power without costing the speed of the circuit and at the same time the complexity is not much. All simulations have been performed at 32 nm process technology on HSPICE tool. It is found that circuit with transmission gate logic gives the best output from the given logics

Keywords: Half adder, delay, power consumption, PDP, EDP

Cite this Article
Ashish Jha, Purushottam Kumawat. Performance Analysis of 1-Bit Half Adder using Different Combinational MOS Logics. Journal of Microelectronics and Solid State Devices. 2017; 4(3): 19–27p