Schmitt-Trigger Based 12T SRAM Cell with Enhanced Stability

Abstract

In this work, we present a single-ended Schmitt-trigger (ST) based 12T static random access memory (SRAM) cell. The proposed cell employs cross-point data aware write structure, and thus supports bit interleaving architecture to mitigate soft errors. The proposed cell does not suffer from read disturbance as bit line is completely isolated from bit storage node. Simulation is done on 180 nm CMOS technology on Cadence. Read static noise margin (RSNM) of the proposed cell is improved by1.42X as compared to conventional 6T bit cell at Vdd=0.7 V. The proposed cell offers 0.0065X lesser write ‘1’ delay as compared to previously proposed ST based 11T SRAM.

Keywords: HSNM, read delay, RSNM, SRAM, write delay, WSNM

Cite this Article

Mansore SR, Gamad RS, Mishra DK. Schmitt-Trigger Based 12T SRAM Cell with Enhanced Stability. Journal of Semiconductor Devices and Circuits. 2018; 5(1): 5–10p.