Open Access Open Access  Restricted Access Subscription or Fee Access

MOS Capacitor: A Processing Tool

Mukesh Maurya, Priya Singh

Abstract


In this modern world of technology, life without electronics is unimaginable. We are now living in the age of electronics. It is hard to find an electrical item in your home that does not have electronics part in it. The electronic devices give better efficiency and reliability in terms of power loss, speed and cost; the fundamental component of each Integrated Circuit (IC) chip, namely the MOSFET (metal oxide semiconductor field effect transistor) needs to be scaled down in size. Device scaling has resulted in unacceptable leakage current in the MOS device because of direct tunnelling of electrons through the gate dielectric. The battery of any electronic device can be discharged rapidly and will produce excessive heat due to the leakage current. Excessive heat produced by all the MOSFET reduces the efficiency. In order to overcome this problem, the oxide of high-k material like hafnium and zirconium are being used to replace the previously used SiO2. As the size of MOS transistor continues to scale-down, the use of SiO2 as a gate dielectric material is approaching the electrical and structural limitation of the material. Regulation of the electrical properties of the MOS system has been one of the crucial aspects that have led to stable and high-performance Si integrated circuit. In this paper, we will study operation of MOS system, how the electrical properties of MOS system are measured, and the result of measurement, how these electrical properties are controlled and how to monitor the electrical property of MOS system during IC fabrication. The MOS capacitor is used in both studying the electrical property of MOS system and monitoring IC fabrication.

 

 


Keywords


High-k dielectric, MOS capacitor, gate tunnelling

Full Text:

PDF

References


Robertson J. Interfaces and Defects of High-K Oxides on Silicon. Solid-State Electron. 2005; 49(3): 283–293p.

Savita Maurya, Sarita Shrivastava. Challenges Beyond 100 nm MOS Devices. Journal of VLSI Design Tools and Technology (JoVDTT). 2016; 6(2): 1–4p.

Savita Maurya, Sarita Shrivastava. Layout Design, Fabrication and Characterization of n-Channel MOSFET. Journal of VLSI Design Tools and Technology (JoVDTT). 2016; 6(2): 13–18p.

Moore GE. Progress in Digital Integrated Electronics [Technical literature, Copyright 1975 IEEE. Reprinted, with permission. Technical Digest. International Electron Devices Meeting, IEEE; 1975; 11–13p]. In IEEE Solid-State Circuits Society Newsletter (SSCS). Sep 2006; 11(3): 36–37p.

Choi KJ, Kim JH, Yoon SG, et al. Structural and Electrical Properties of HfOxNy and HfO2Gate Dielectrics in TaN Gated nMOSCAP and nMOSFET Devices. J Vac Sci Technol B. 2004; 22: 1755–1758p.

Wilk D, Wallace RM, Anthony JM. High-k Gate Dielectrics: Current Status and Materials Properties Considerations. J Appl Phys. May 2001; 89(10): 5243–5275p.

Maurya S. Study of Atomic Layer Deposited HfO2/Si Interfaces for Their Quality, Reliability and Radiation Based Interface Modifications. Ph.D. Dissertation (IIIT-Allahabad, India. 2015.

Zhu WJ, Tamagawa T, Gibson M, et al. Effect of Al Inclusion in HfO2 on the Physical and Electrical Properties of the Dielectrics. IEEE Electron Device Lett. 2002; 23(11): 649–651p.

Houssa M, Pantisano L, Ragnarsson L, et al. Electrical Properties of High-κ Gate Dielectrics: Challenges, Current Issues, and Possible Solutions. Mater Sci Eng R Rep.2006; 51(4–6):37–85p.

Maurya S, Tribedi LC, Radhakrishna M. Engineering of Silicon/HfO2Interface by Variable Energy Proton Irradiation. Appl Phys Lett. 2014; 105(7):071605: 1-4p.

M Rasras, De Wolf, G Groeseneken, et al. Photo-Carrier Generation as the Origin of Fowler-Nordheim-Induced Substrate Hole Current in Thin Oxides. International Electron Devices Meeting. Technical Digest (Cat. No.99CH36318), Washington, DC, USA, 1999, 465-468p.

Di Maria DJ, Cartier E, Buchanan DA. Anode Hole Injection and Trapping in Silicon Dioxide. J Appl Phys. 1996; 80(1): 304–317p.

Dumin DJ, Maddux JR, Scott RS, et al. A Model Relating Wear Out to Breakdown in Thin Oxides. IEEE Trans Electron Devices. 1994; 41(9): 1570–1580p.

Maurya S. Silicon/ HfO2 Interface: Effects of Gamma Irradiation. AIP Conf Proc. 2016; 1731(1): 120034p.

Kang AY, Lenahan PM, Conley JF. The Radiation Response of the High Dielectric-Constant Hafnium Oxide/ Silicon System. IEEE Trans Nucl Sci. 2002; 49(6): 2636–42p.

Maurya S. Silicon/HfO2 Interface: Effects of Proton Irradiation. AIP Conf Proc. 2015; 1665(1): 120041: 1-3p.

Holmes-Siedle AG, Adams L. Handbook of Radiation Effects. 2nd Edn. New York: Oxford University Press; 2002.

Maurya S. Effect of Zero Bias Gamma Ray Irradiation on HfO2 Thin Films. J Mater Sci: Mater Electron. 2016; 27(12): 12796–12802p.

Maurya S. Interface Modification by Irradiation with Alpha Particles. J Mater Sci: Mater Electron. 2017; 28(23): 17442–17447p.

Lee WC, King T-J, Hu C. Observation of Reduced Boron Penetration and Gate Depletion for Poly-SiGe Gated PMOS Devices. IEEE Electron Dev Lett. 1999; 20(1): 9–11p.

Size SM. Physics of Semiconductor Devices. New York: Wiely; 1969.

Maurya S, Singh BR, Radhakrishna M. Impact of Fringing Field on the C-V Characterization of HfO2, High-K Dielectric MOS (p) Capacitors Fabricated through Atomic Layer Deposition. AIP Conference Proceedings. 2013; 1512(1): 742-743p.

Maurya S, Singh BR, Radhakrishna M. Effect of Pre-Deposition Annealing on the Performance of MIS Capacitor Formed Using Atomic Layer Deposition of Ultrathin HfO2. AIP Conf Proc. 2013; 1536(1): 1159-1160p.

Maurya S, Singh BR, Radhakrishna M. Analysis of Leakage Current in Extremely Scaled HfO2 Gate Stack Deposited by ALD. IMPACT: Int J Res Eng Technol. 2014; 2(3): 121–128p.

Maurya S. Effect of Nitrogen Passivation/ Pre-Nitration on Interface Properties of Atomic Layer Deposited HfO2. J Mater Sci: Mater Electron. 2018; 29(9), 7917-7923p.

https://doi.org/10.1007/s10854-018-8791-z.




DOI: https://doi.org/10.37591/josdc.v5i1.562

Refbacks

  • There are currently no refbacks.


Copyright (c) 2018 Journal of Semiconductor Devices and Circuits

Publisher: STM Journals, an imprint of CELNET (Consortium e-Learning Network Pvt. Ltd.)

Address: A-118, 1st Floor, Sector-63, Noida, Uttar Pradesh-201301, India

Phone no.: 0120-478-1215/ Email: [email protected]