4-Bit Magnitude Comparator Design using Different Logic Styles

Abstract

4-Bit Magnitude Comparator using various logic styles is explained here. Comparison is one of the common arithmetic operations that is used to determine which number is greater, equal to, or less. Every device from OP-AMP to ALU needs to perform comparison operations. At designing level, comparator can be designed by using different logic styles. Here, comparison is done for simple 4-Bit combinational comparator and cascaded comparator which we have designed and have calculated the power and delay for both the designs. Results for both the designs are presented in the form of simulations that is performed on Cadence virtuoso at 180 nm technology at different voltages.

Keywords: Comparator, arithmetic, virtuoso, cascaded, power, delay

Cite this Article

Vipul Mittal, Tanushree, Madhulika Arora, Meenakshi Yadav, Sakshi Chaudhary. 4-Bit Magnitude Comparator Design Using Different Logic Styles, Journal of VLSI Design Tools and Technology. 2015; 5 (2): 16–22p.