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Automated Access Backdoor for UVM_REG Layer

Seep Sethi, Neeraj Kr. Shukla

Abstract


Systems on chips (SoCs) design have many configuration registers. Configuring the registers through a Bus protocol consumes lot of simulation time. Hence, time saving becomes a challenge in configuring the registers. The other way to configure registers is backdoor access. Backdoor is a zero simulation time access by mapping to the register directly using the hierarchical path. It allows rapid configuration of registers and can uncover hidden bugs as execution of write and read cycles are occur on same access path. Backdoor is much faster than front door. For backdoor access, the user needs the hierarchical path of the register. In order to achieve that user can either search register in design hierarchy or can communicate with the RTL designer. Complexity of determining hierarchical path is reduced by automating the backdoor access for UVM_REG which will capture the hierarchical path of the register at the run time simulation. This capturing of register at the run time simulation can be done through Programming Language Interface (PLI).

Keywords: Backdoor, Gnumeric, PLI, Python, UVM_REG


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eISSN: 2249–474X