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An Innovative Approach of the Analysis of the Low Noise of a CMOS-Based Amplifier for Analog Signal-based Applications

rajinder tiwari, R. K. Singh

Abstract


A low-noise amplifier (LNA), which is based on the cascode feedback methodology, has been commonly used for various wireless protocol-based network applications nowadays. It is so because this topology ensures that the low-noise amplifier (LNA) can achieve quite a high performance and thus, provides a high qualitative output. This amplifier is operated with a low voltage supply in the range of few volts that requires that the impedances of the input and the output to be rather of matched value so as to provide the output with minimum possible noise distortion. Thus, based on this concept/approach, an innovative approach of the design methodology for the design of a CMOS-based low-noise amplifier (CLNA) has been put forward for discussing the performance of the system. Now, in this efficient procedure of the design of CLNA, one has to consider the effective behavior of certain dominant parameters of the circuit such as noise figure, gain, linearity, channel length, etc. The simulation work of the proposed LNA has been carried out with pSpice software using the level 3 parameters based on 0.13 µm CMOS technology that provides the desired outputs. From these experimental results, it has been observed that with the input referred noise of the proposed amplifier 2.5 nV/Hz, the bandwidth of the circuit is in the range of 1 GHz, the power dissipation due to various devices is about 160 μW, with 0.5 dB of low-noise figure and the power consumption in the circuit is as low as 7.0 mW.

 

Keywords: Low-noise amplifier (LNA), CLNA, CMOS devices, noise figure, pSpice, induced gate noise, CMOS-based amplifier, passive network


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