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A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique

B S Patro, srinibasa padhy, monica swain, J K Das


In the present arena of technology scaling, the power consumption in the deep submicron technology plays a pivotal role as the transistor counts increases dramatically. Therefore, the need of the hour is to focus on power dissipation. The rate of occurrences of errors in the present VLSI scenarios has become higher and inevitable, and is increasing along with technology scaling. Eradicating all the errors is a cumbersome task; still a semi accurate result in better performance instead of accurate one can be accepted in some specific applications. An error tolerance adder is one such application specific adder to overcome the power delay trade-off by eradicating carry propagation and introducing a little error. To further enhance its efficiency and performance, GDI technique is introduced. In this paper, the GDI based architecture of probabilistic error tolerant adder (III) has been introduced, thus inferring the simulation with much more reduced power, delay and enormously enhanced performance over conventional adder.


Keywords: Error tolerance, gate diffusion input, full adder

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