Open Access Open Access  Restricted Access Subscription or Fee Access

Characterization of Low Power-Low Jitter Digital PLL

Nilesh D. Patel, Amisha P. Naik


The architecture design is being done in transistor level and tool which supports transistor level design. Mentor Graphics Tool is used for transistor level design and its simulation design. There are few tools which support design simulation like HSpice, Spectre and PSpice. Also a foundry support is from Taiwan Semiconductor Manufacturing Corporation (TSMC) (i.e.) technology model files 180 nm from TSMC for simulation. This article presents design for 1.5 GHz phase locked loop in 180 nm CMOS technology. Phase noise of proposed design is –87.64 dBc/Hz at 1 MHz reference offset frequency. Total power dissipation of PLL is 6.92 mW and RMS jitter is 1.09 ns in locked condition.

Keywords: CMOS, PLL, loop filter, voltage control oscillator, phase frequency detector

Cite this Article
Patel Nilesh D, Naik Amisha P. Characterization of Low Power-Low Jitter Digital PLL. Journal of VLSI Design Tools & Technology. 2018; 8(2): 23–32p.


CMOS, PLL, Loop Filter, Voltage Control Oscillator, Phase Frequency Detector

Full Text:



Mhd Zaher Al Sabbagh, B.S., “0.18μm Phase / Frequency Detector and Charge Pump Design for Digital Video Broadcasting for Handheld’s Phase-Locked-Loop Systems”, The Ohio State University, 2007.

N. Pavlovic, J. Gosselin, K. Mistry and D. Leenaerts (2004), A 10 GHz frequency synthesizer for 802.11a in 0.18 μm CMOS, Solid-State Circuits Conference 2004, 367-370.

T.-H. Lin and Y.-J. Lai (2007), An agile VCO frequency calibration technique for a 10-GHz CMOS PLL, IEEE J. Solid-State Circuits 42 (2), 340-349.

Ana Armendáriz Hugalde, “Analysis and Design of PFDs in Cadence”, Thessaloniki 2010.

Sai, A.; Kobayashi, Y.; Saigusa, S.; Watanabe, O.; Itakura, T., “A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS”, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE.

Roland E. Best, “Phase Locked Loops, Design, Simulation and Applications”, TMH Publication, 2003.

Evan Lee Eschenko, “A Low Power Prescaler, Phase Frequency Detector, and Charge Pump for a 12 Ghz Frequency Synthesizer”, Texas A&M University, December 2007.

Won – Hyo Lee, Jun – Dong Cho, Sung – Dae Lee, “A High Speed and Low Power Phase-Frequency Detector and Charge – Pump”, 2010.

Gaetano Palumbo (IEEE Fellow) and Domenico Pappalardo IEEE CIRCUITS AND SYSTEMS MAGAZINE, Universitá di Catania, Viale Andrea Doria 6, I-95125, Catania, Italy.

Karutharaja.v, M. Bhaskar, Dr. B. Venkataramani, Synchronization of On-chip Serial Interconnect Transceivers using Delay Locked Loop (DLL), International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011), IEEE,2011.

Siliang Hua, Hua Yang, Yan Liu, Quanquan Li1, Donghui Wang, A Power and Area Efficient CMOS Charge-Pump Phase-Locked Loop, IEEE, 2012.

B. P. Panda, P. K. Rout, D. P. Acharya and G. Panda , “Design of a Novel Current Starved VCO via Constrained Geometric Programming” , International Symposium on Devices MEMS Intelligent Systems Communications, April 12-14,2011.



  • There are currently no refbacks.

Copyright (c) 2018 Journal of VLSI Design Tools & Technology

eISSN: 2249–474X