High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography

Abstract

In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman algorithm; an efficient modular adder without comparison and a high throughput modular divider using GCD, which results in a short data path for maximum frequency, Processor arithmetic operation consist of 256 bits. This proposed processor supports P256 NIST prime field curve standards using Xilinx 14.7 software we analyze logic size, area and power consumption.

Keywords: Application-specific instruction-set processor (ASIP), elliptic curve cryptography (ECC), field programmable gate array (FPGA), Karatsuba-Ofman multiplication, redundant signed digit (RSD), Greatest common divisor (GCD)

Cite this Article
Abhay Arvind Koparde, K. Sujatha. High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography. Journal of VLSI Design Tools & Technology. 2017; 7(3): 45–50p.