Journal of VLSI Design Tools & Technology (JoVDTT)

Vol 6, No 1 (2016)

Open Access  Subscription or Fee Access

Table of Contents

Articles

A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit M. Hulkey, H. Upadhyay, K. Sujhatha

PDF 1-5

Hardware Implementation of Configurable Multi Image Fusion S S. Malwadkar, W M. Mendre, S S. Agrawal

PDF 6-15

A Review for Power Optimization in MOS Devices using Different Logic Styles M. Hulkey, H. Upadhyay, K. Sujatha

PDF 16-20

Simulation Study of Tapered Shape FinFET A. Shrivastava, S. Singh, A. Acharya, G Musalgaonkar

PDF 21-31

Switched Capacitor-based RC Filter jinal A prajapti, Mehul L Patel

PDF 32-40

Cluster Based Sleep Transistor Approach for Low Power 6T SRAM Cell P. Raikwal, V. Neema, A. Verma

PDF 41-48

Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence J. K. Arya, A. Raman

PDF 49-54

Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-simulation akash mecwan, bhupendra fataniya, dhaval shah

PDF 55-61

Modeling of Voltage Buffer and Memristor Voltage Buffer Using 180 nm Technology Herman Al Ayubi, navaid Z. rizvi, piyush K. Mishra

PDF 62-72

Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell Jitendra Krishna Arya, Ashish Raman

PDF 73-77

GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology jubal saji, shoaib kamal

PDF 78-88

A Differentiator Based on Second Generation Current Controlled Conveyor A. Kumar, R. Pandey

PDF 89-95

eISSN: 2249–474X