Journal of VLSI Design Tools & Technology (JoVDTT)

Vol 6, No 2 (2016)

Open Access  Subscription or Fee Access

Table of Contents

Articles

Challenges Beyond 100 nm MOS Devices savita maurya, sarita Shrivastava

PDF 1-4

Design and Performance Trends of Low Power Sigma-Delta A/D Converters saima bashir, suhaib ahmed, vipan kakkar

PDF 5-12

Layout Design, Fabrication and Characterization of n-Channel MOSFET savita maurya, savita Shrivastava

PDF 13-18

Comparative Analysis of MOSFET, CNTFET and NWFET for High Performance VLSI Circuit Design: A Review sanjeev kumar sharma, balwinder raj, mamta khosla

PDF 19-32

Design and Implementation of Low Power 8-bit Level Crossing ADC vaishali gupta, anil kumar gupta

PDF 33-43

Design and RTL Implementation for AHB-APB Bridge on SoC shipra sharma, rakhi nangia, neeraj kumar shukla

PDF 44-52

Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique archana kumari, navdeep prashar

PDF 53-61

Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM ashima gandhi, neeraj kr. shukla

PDF 62-73

A New TGC-Differential Input Stage to Modify Dynamic Comparator anurag sharma, gurinderpal singh

PDF 74-85

Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power Vijay Savani, N M Devashrayee

PDF 86-98

Implementation and Simulation of High-Speed Dynamic Latch Comparator for ADC jatin A. jalal, mehul L Patel

PDF 99-103

Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog ashima gandhi, neeraj kr. shukla

PDF 104-112

eISSN: 2249–474X