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Issue Title
 
Vol 5, No 2 (2015) 4-Bit Magnitude Comparator Design using Different Logic Styles Abstract
Vipul Mittal, Tanushree ., Madhulika Arora, Meenakshi Yadav, Sakshi Chaudhary
 
Vol 8, No 2 (2018) A Common Mode Scan Based BIST for Stuck-at-Fault and Path Delay Fault Abstract
Ram Vishnu S, Yasodha T
 
Vol 8, No 3 (2018) A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions Abstract
Pratiksha Kharat
 
Vol 5, No 2 (2015) A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier Abstract
Kirti Sharma, Anushree .
 
Vol 5, No 3 (2015) A Review on Charge Pump Circuits for PLL Applications Abstract
D. Shekhar, A. Raman
 
Vol 8, No 2 (2018) A Review on FPGA Parallel Architecture for Object Detection Abstract
Sudhir Dagar, Geeta Nijhawan
 
Vol 8, No 2 (2018) A Review on Tunnel Field Effect Transistor for Ambipolar Suppression, Higher ON Current and a Lower Subthreshold Swing Abstract
Radhika M. Somani, H. R. Upadhyay, K. Sujatha
 
Vol 8, No 3 (2018) A Time Domain Analysis on Chip High Speed VLSI Optical Interconnection Network Abstract
Abhishek Sharma, Sudhir Kumar Sharma
 
Vol 5, No 3 (2015) All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey Abstract
Rajesh Yadav, Neeraj Kumar Shukla, Rajesh Gupta
 
Vol 8, No 3 (2018) An Area Delay Optimized Carry-Select Adder Abstract
Sareeka Tulshiram Deore
 
Vol 8, No 2 (2018) Area and Power Improvement with New Initial Ordering Method Combined with Sift Algorithm for BDD Mapped Circuits Abstract
M. Balal Siddiqui, M. T. Beg, S. Naseem Ahmad
 
Vol 5, No 2 (2015) Automated Access Backdoor for UVM_REG Layer Abstract
Seep Sethi, Neeraj Kr. Shukla
 
Vol 8, No 1 (2018) AXI Bridge and DMA/Bridge Subsystem for PCIe Abstract
Shivani Malhotra, Neelam Rup Prakash
 
Vol 7, No 3 (2017) Carbon Nanotube Transistor Based Novel Ring Oscillator with Minimum Power Consumption at 32 nm Technology Node Abstract   PDF
Chandramohan K, Nikhil Saxena, Sapna Navre, Sonal Soni
 
Vol 5, No 2 (2015) Characterization of High Performance Third Generation Current Conveyor using CMOS Technology Abstract
Megha M. Patel, Nilesh D. Patel
 
Vol 5, No 1 (2015) Characterization of High Speed Phase Frequency Detector Circuit Abstract
Nilesh D. Patel, Amisha P. Naik
 
Vol 8, No 2 (2018) Characterization of Low Power-Low Jitter Digital PLL Abstract
Nilesh D. Patel, Amisha P. Naik
 
Vol 8, No 3 (2018) Circular Retiming technique to design Optimized Least Mean square architecture for adaptive filter Abstract
Jalaja S., Vijaya Prakash A. M
 
Vol 5, No 3 (2015) CMOS Gm-C IF Filter using SCA for Dual Band Receiver Abstract
Kehul A. Shah, NM Devashrayee
 
Vol 5, No 2 (2015) Comparative Analysis of Class-AB Voltage Follower using DTMOS Transistor Abstract
Nishtha K. Patel, Nilesh D. Patel
 
Vol 8, No 1 (2018) Comparative Analysis of Combinational Circuit Using Reversible Logic Based Techniques Abstract
Aakriti Dawarand, Bal Krishan
 
Vol 8, No 2 (2018) Comparative Analysis of Different SRAM Cells Architecture at 70 nm Abstract
Nidhi Tiwari, Vaibhav Neema, Kamal J. Rangra, Yogesh Chandra Sharma
 
Vol 5, No 2 (2015) Comparative Analysis of High Speed Comparator for A to D Converters Abstract
Priyesh Gandhi, Neha B. Rathod, N. M. Devashrayee
 
Vol 5, No 2 (2015) Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter Abstract
Aakansha Barala, Pooja Sabherwal, Meenakshi Yadav
 
Vol 5, No 2 (2015) Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology Abstract
A.K. Pathrikar, Rajkumar S. Deshpande
 
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