Browse Title Index

Issue Title
Vol 8, No 2 (2018) A Common Mode Scan Based BIST for Stuck-at-Fault and Path Delay Fault Abstract
Ram Vishnu S, Yasodha T
Vol 8, No 2 (2018) A Review on FPGA Parallel Architecture for Object Detection Abstract
Sudhir Dagar, Geeta Nijhawan
Vol 8, No 2 (2018) A Review on Tunnel Field Effect Transistor for Ambipolar Suppression, Higher ON Current and a Lower Subthreshold Swing Abstract
Radhika M. Somani, H. R. Upadhyay, K. Sujatha
Vol 8, No 2 (2018) Area and Power Improvement with New Initial Ordering Method Combined with Sift Algorithm for BDD Mapped Circuits Abstract
M. Balal Siddiqui, M. T. Beg, S. Naseem Ahmad
Vol 8, No 1 (2018) AXI Bridge and DMA/Bridge Subsystem for PCIe Abstract
Shivani Malhotra, Neelam Rup Prakash
Vol 7, No 3 (2017) Carbon Nanotube Transistor Based Novel Ring Oscillator with Minimum Power Consumption at 32 nm Technology Node Abstract   PDF
Chandramohan K, Nikhil Saxena, Sapna Navre, Sonal Soni
Vol 8, No 2 (2018) Characterization of Low Power-Low Jitter Digital PLL Abstract
Nilesh D. Patel, Amisha P. Naik
Vol 8, No 1 (2018) Comparative Analysis of Combinational Circuit Using Reversible Logic Based Techniques Abstract
Aakriti Dawarand, Bal Krishan
Vol 8, No 2 (2018) Comparative Analysis of Different SRAM Cells Architecture at 70 nm Abstract
Nidhi Tiwari, Vaibhav Neema, Kamal J. Rangra, Yogesh Chandra Sharma
Vol 8, No 2 (2018) Design of Three-Stage Pipelined Floating Point Arithmetic Operators Abstract
Shaikh Shoaib Arif, B. B. Godbole
Vol 7, No 3 (2017) Effect of Various Parameters on Threshold Voltage of Virtually Fabricated Lightly Doped PMOS Device Abstract   PDF
Nitin Sachdeva, Munish Vashishath, P. K. Bansal
Vol 8, No 1 (2018) Fault Detection Attainment for Embedded Cores based on Software Test Routines Abstract
Vishal Gangadhar Puranik, Dilip Devchand Shah
Vol 8, No 2 (2018) High Gain Antenna Array (2x1 and 4x1) Design for WLAN Application Abstract
Devendra Sharma, Charanjeet Singh
Vol 7, No 3 (2017) High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography Abstract   PDF
Abhay Arvind Koparde, K. Sujatha
Vol 8, No 1 (2018) High Speed and Low Power Basic Digital Logic Gates, Half-Adder and Full-Adder Using Modified Gate Diffusion Input Technology Abstract
Khoirom Johnson Singh, Tripurari Sharan, Huirem Tarunkumar
Vol 8, No 1 (2018) High Speed Low Offset Power Efficient Fully Differential Double Tail Dynamic Comparator Abstract
Priyesh Gandhi, N. M. Devashrayee
Vol 7, No 3 (2017) Implementation of RSA and CRT-RSA with MIST to Resist Power Analysis Attacks Abstract   PDF
Hridoy Joy Mahanta, Ajoy Kumar Khan
Vol 8, No 2 (2018) Investigation and Dependency Analysis of Silicon Film Thickness on Performance of Surrounding Gate MOSFET at Subthreshold Regime Abstract
Tarun Kumar Sachdeva, S. K. Agarwal, Alok K. Kushwaha
Vol 7, No 3 (2017) Low Power High Speed Eight-Transistor (8T) SRAM Cell with Enhanced Data Stability Abstract   PDF
P. Raikwal, V. Neema, A. Verma
Vol 7, No 3 (2017) Low-Offset High Speed CMOS Voltage Comparator using 180 nm Technology Abstract   PDF
Rohitkumar M. Joshi, Priyesh P. Gandhi
Vol 8, No 1 (2018) Memristor based Material Implication Logic for Implementation of Basic logic Gates and Circuits Abstract
Rita Mahajan, Basudha Dewan, Deepak Bagai
Vol 7, No 3 (2017) Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology Abstract   PDF
Bharat Tripathi, Saurabh Khandelwal
Vol 8, No 1 (2018) Review Paper To Design a Low Power CNTFET Based XOR Gate Abstract
Veski Dabas, Surender Kumar Grewal
Vol 8, No 1 (2018) Review Paper: Low Power SRAM Cell using FinFET Technology Abstract
Mamta ., Surender Kumar Grewal
Vol 7, No 3 (2017) Single Bit Low-Power High-Speed Full Adder Abstract   PDF
Sachin Pandurang Gaikwad, Sujatha Kondakinda, Harsh Upadhyay
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