Browse Title Index


 
Issue Title
 
Vol 5, No 2 (2015) 4-Bit Magnitude Comparator Design using Different Logic Styles Abstract
Vipul Mittal, Tanushree ., Madhulika Arora, Meenakshi Yadav, Sakshi Chaudhary
 
Vol 8, No 2 (2018) A Common Mode Scan Based BIST for Stuck-at-Fault and Path Delay Fault Abstract
Ram Vishnu S, Yasodha T
 
Vol 4, No 2 (2014) A Cuckoo Search based Approach for Solving Standard Cell Placement Problem Abstract
amanpreet singh, maninder kaur
 
Vol 6, No 1 (2016) A Differentiator Based on Second Generation Current Controlled Conveyor Abstract
A. Kumar, R. Pandey
 
Vol 8, No 3 (2018) A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions Abstract
Pratiksha Kharat
 
Vol 3, No 1 (2013) A High Performance Reference Circuit with Optimized Input Offset Operational Amplifier using Device Mismatch Model Abstract
Anil K. Saini, Kapil K. Rajput, Sanjay Singh, Ravi Saini
 
Vol 4, No 3 (2014) A Low Power Variable Gain Amplifier for Biomedical Application Abstract
dipesh panchal, amisha naik, N M Devshrayee
 
Vol 4, No 1 (2014) A New Current Mode Quadrature Oscillator using Current Differencing Transconductance Amplifier (CDTA) Abstract
Sajal K. Paul
 
Vol 3, No 1 (2013) A New High Speed Low Power 1 Bit Full Adder Abstract
Angshuman Chakraborty, Sambhu Nath Pradhan
 
Vol 3, No 1 (2013) A New Sub-1 Volt Reference for Low Voltage Application Based on MOSFET’s Threshold Voltage Extractor Abstract
Anil K. Saini, Megha Agarwal
 
Vol 6, No 2 (2016) A New TGC-Differential Input Stage to Modify Dynamic Comparator Abstract
anurag sharma, gurinderpal singh
 
Vol 3, No 3 (2013) A Novel 4:1 Multiplexer Design using Power Minimization Technique based Domino Logic Abstract
Vignesh M, Naveen R
 
Vol 7, No 1 (2017) A Novel Approach Based On-Chip High Speed Optical Interconnection Network Abstract
abhishek sharma, sudhir kumar sharma, pramod sharma
 
Vol 7, No 1 (2017) A Novel Approach for 3D Floor Planning in VLSI with Minimum Dead Space using a New Topological Structure Abstract
ajoy kumar khan
 
Vol 4, No 2 (2014) A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture Abstract
ashish s shende, deepak r dandekar
 
Vol 4, No 1 (2014) A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology Abstract
Vijayanand K, Sureshkumar N
 
Vol 5, No 2 (2015) A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier Abstract
Kirti Sharma, Anushree .
 
Vol 6, No 1 (2016) A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit Abstract
M. Hulkey, H. Upadhyay, K. Sujhatha
 
Vol 6, No 1 (2016) A Review for Power Optimization in MOS Devices using Different Logic Styles Abstract
M. Hulkey, H. Upadhyay, K. Sujatha
 
Vol 5, No 3 (2015) A Review on Charge Pump Circuits for PLL Applications Abstract
D. Shekhar, A. Raman
 
Vol 8, No 2 (2018) A Review on FPGA Parallel Architecture for Object Detection Abstract
Sudhir Dagar, Geeta Nijhawan
 
Vol 8, No 2 (2018) A Review on Tunnel Field Effect Transistor for Ambipolar Suppression, Higher ON Current and a Lower Subthreshold Swing Abstract
Radhika M. Somani, H. R. Upadhyay, K. Sujatha
 
Vol 4, No 2 (2014) A Simple, Compact, and Power-Efficient Current-Mode Decimal Adder Circuit Abstract
ashish s shende
 
Vol 4, No 2 (2014) A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated Circuits Abstract
harshvardhan upadhyay
 
Vol 8, No 3 (2018) A Time Domain Analysis on Chip High Speed VLSI Optical Interconnection Network Abstract
Abhishek Sharma, Sudhir Kumar Sharma
 
1 - 25 of 171 Items 1 2 3 4 5 6 7 > >>