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Issue Title
 
Vol 8, No 2 (2018) Characterization of Low Power-Low Jitter Digital PLL Abstract
Nilesh D. Patel, Amisha P. Naik
 
Vol 8, No 3 (2018) Circular Retiming technique to design Optimized Least Mean square architecture for adaptive filter Abstract
Jalaja S., Vijaya Prakash A. M
 
Vol 6, No 1 (2016) Cluster Based Sleep Transistor Approach for Low Power 6T SRAM Cell Abstract
P. Raikwal, V. Neema, A. Verma
 
Vol 5, No 3 (2015) CMOS Gm-C IF Filter using SCA for Dual Band Receiver Abstract
Kehul A. Shah, NM Devashrayee
 
Vol 3, No 2 (2013) Cogeneration of Fast Motion Estimation Processor and Algorithms Using Loss Less Compression Abstract
M. Viji, S. Chitra
 
Vol 5, No 2 (2015) Comparative Analysis of Class-AB Voltage Follower using DTMOS Transistor Abstract
Nishtha K. Patel, Nilesh D. Patel
 
Vol 8, No 1 (2018) Comparative Analysis of Combinational Circuit Using Reversible Logic Based Techniques Abstract
Aakriti Dawarand, Bal Krishan
 
Vol 8, No 2 (2018) Comparative Analysis of Different SRAM Cells Architecture at 70 nm Abstract
Nidhi Tiwari, Vaibhav Neema, Kamal J. Rangra, Yogesh Chandra Sharma
 
Vol 5, No 2 (2015) Comparative Analysis of High Speed Comparator for A to D Converters Abstract
Priyesh Gandhi, Neha B. Rathod, N. M. Devashrayee
 
Vol 4, No 2 (2014) Comparative Analysis of Low-Power Adiabatic Techniques Abstract
charu rana, priyanka ojha
 
Vol 6, No 2 (2016) Comparative Analysis of MOSFET, CNTFET and NWFET for High Performance VLSI Circuit Design: A Review Abstract
sanjeev kumar sharma, balwinder raj, mamta khosla
 
Vol 7, No 1 (2017) Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops Abstract
Gunjankumar R Modi, Priyesh P Gandhi, Nilesh D Patel
 
Vol 3, No 2 (2013) Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder Abstract
Ankit Mitra
 
Vol 5, No 2 (2015) Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter Abstract
Aakansha Barala, Pooja Sabherwal, Meenakshi Yadav
 
Vol 2, No 1-2-3 (2012) Decimator Design for Sigma-Delta ADC Abstract
Narendra Bahadur Singh, tripti sharma, prashant singh
 
Vol 2, No 1-2-3 (2012) Delay Minimization of 3 Cascaded Inverters with the Help of Logical Effort and Transistor Sizing Abstract
sampath kumar, neerja singh
 
Vol 5, No 2 (2015) Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology Abstract
A.K. Pathrikar, Rajkumar S. Deshpande
 
Vol 4, No 2 (2014) Design and Analysis of Energy-Efficient GDI Cell and Its Impact on Multipliers Abstract
preethi rangaraj, naveen raman
 
Vol 8, No 3 (2018) Design and Analysis of MAC Unit Using Single Precision Floating Point Vedic Multiplier Abstract
Athira A D, Anjaly Krishnan
 
Vol 3, No 3 (2013) Design and Analysis of Source Current Effect on Preamplifier-Positive Feedback-based CMOS Comparator Using 90 nm Technology Abstract
Vijay Savani, NM Devashrayee
 
Vol 4, No 1 (2014) Design and Implementation of 2nd Order Gm-C IF Tuning Filter Operating at 900 MHz and 88–108 MHz Wireless System for Multi Standard Receiver Abstract
Kehul A. Shah, N M Devashrayee
 
Vol 5, No 3 (2015) Design and Implementation of an Efficient Ternary Control Unit Abstract
Satish S. Narkhede, BS Chaudhari, GK Kharate
 
Vol 4, No 3 (2014) Design and Implementation of Low Noise Amplifier using 90 nm MOS Technology for Bluetooth Abstract
akash mecwan, nikunj marodiya, vimal zalariya
 
Vol 6, No 2 (2016) Design and Implementation of Low Power 8-bit Level Crossing ADC Abstract
vaishali gupta, anil kumar gupta
 
Vol 5, No 3 (2015) Design and Performance Analysis of Multi-Standard CMOS LNA Using Switched Capacitor and MIM Capacitor in 180nm Technology Abstract
Nishant Poras, Priyanka Goyal
 
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