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Issue Title
 
Vol 6, No 1 (2016) Hardware Implementation of Configurable Multi Image Fusion Abstract
S S. Malwadkar, W M. Mendre, S S. Agrawal
 
Vol 5, No 2 (2015) Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave Abstract
Pragya Sharma, Neeraj Kr. Shukla, Rakhi Nangia
 
Vol 8, No 2 (2018) High Gain Antenna Array (2x1 and 4x1) Design for WLAN Application Abstract
Devendra Sharma, Charanjeet Singh
 
Vol 7, No 3 (2017) High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography Abstract   PDF
Abhay Arvind Koparde, K. Sujatha
 
Vol 7, No 2 (2017) High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography Abstract
Abhay Arvind Koparde, K. Sujatha
 
Vol 8, No 1 (2018) High Speed and Low Power Basic Digital Logic Gates, Half-Adder and Full-Adder Using Modified Gate Diffusion Input Technology Abstract
Khoirom Johnson Singh, Tripurari Sharan, Huirem Tarunkumar
 
Vol 8, No 1 (2018) High Speed Low Offset Power Efficient Fully Differential Double Tail Dynamic Comparator Abstract
Priyesh Gandhi, N. M. Devashrayee
 
Vol 2, No 1-2-3 (2012) High-speed CMOS ADCs Design Abstract
Narendra Bahadur Singh, prashant singh
 
Vol 5, No 1 (2015) Hybrid CMOS-SET Inverter Design for Improved Performance using Tied Body-backgate Technique Abstract
Prashant Gupta, Shashank Kumar Ranu, Manish Kumar Pandey, Aminul Islam
 
Vol 9, No 1 (2019) Implementation and Analysis of 32-bit pipelined RISC Processor Architecture Abstract
P. Indira, M. Kamaraju
 
Vol 6, No 2 (2016) Implementation and Simulation of High-Speed Dynamic Latch Comparator for ADC Abstract
jatin A. jalal, mehul L Patel
 
Vol 4, No 3 (2014) Implementation and Simulation of MOSFET Switch for Switched Capacitor Circuits Abstract
mehul l patel, N M Devashrayee
 
Vol 7, No 1 (2017) Implementation of Carry Select Adder with Reduced Area Scheme Abstract
pinaki satpathy
 
Vol 9, No 2 (2019) Implementation of DCC technique using differential amplifier based filter in 90nm CMOS technology Abstract   PDF
Lalita Machhindra Landge, Usha Jadhav
 
Vol 9, No 1 (2019) Implementation of Different Low Power Techniques on CMOS Inverter and NAND Circuits Abstract
Karishma Yadav, Vandana Khanna, Gaurav Shingwani, Ishita Ishita
 
Vol 6, No 1 (2016) Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-simulation Abstract
akash mecwan, bhupendra fataniya, dhaval shah
 
Vol 6, No 2 (2016) Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique Abstract
archana kumari, navdeep prashar
 
Vol 7, No 3 (2017) Implementation of RSA and CRT-RSA with MIST to Resist Power Analysis Attacks Abstract   PDF
Hridoy Joy Mahanta, Ajoy Kumar Khan
 
Vol 7, No 2 (2017) Implementation of RSA and CRT-RSA with MIST to Resist Power Analysis Attacks Abstract
Hridoy Jyoti Mahanta, ajoy kumar khan
 
Vol 8, No 2 (2018) Investigation and Dependency Analysis of Silicon Film Thickness on Performance of Surrounding Gate MOSFET at Subthreshold Regime Abstract
Tarun Kumar Sachdeva, S. K. Agarwal, Alok K. Kushwaha
 
Vol 6, No 2 (2016) Layout Design, Fabrication and Characterization of n-Channel MOSFET Abstract
savita maurya, savita Shrivastava
 
Vol 6, No 3 (2016) Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers Abstract
akash I mewan, N M Devashrayee
 
Vol 3, No 2 (2013) Logic Optimization Algorithm based on Shannon’s Expansion: Reduction in Area, Power and Delay for Pass Gate Implementation Abstract
Usha Sandeep Mehta, Vaishali Dhare, Harikrishna Parmar, Rahul A. Shah
 
Vol 4, No 1 (2014) Low Power 8-Bit Square Root Carry Select Adder Constructed By Using 8 Transistor Full Adder Abstract
A unmai
 
Vol 7, No 3 (2017) Low Power High Speed Eight-Transistor (8T) SRAM Cell with Enhanced Data Stability Abstract   PDF
P. Raikwal, V. Neema, A. Verma
 
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