Numerical Simulation-based Comparative Study of P3HT-based Top Contact and Bottom Contact OTFTs

Authors

  • Arun Dev Dhar Dwivedi Department of Electrical and Electronics Engineering, Poornima University Jaipur
  • S.K. Jain
  • Shubham Dadhich

DOI:

https://doi.org/10.37591/joedt.v10i3.3390

Abstract

Abstract

In this paper presents numerical simulation-based comparative study of bottom and top contact configurations of P3HT based organic thin-film transistor (OTFT). I-V characteristics has been evaluated using the TCAD simulator and comparison of the performance parameters of these devices has been presented. The dimensions of the transistors for all the proposed structures are kept the same for a valid comparison between them. The observed results were explained based on the significantly reduced area of the injection and carrier extraction regions in the source/channel and channel/drain interfaces in the lower contact transistor, with consequent performance degradation compared to the top contact transistor.

Keywords: Poly (3-hexylthiophene) P3HT, organic thin-film transistors (OTFTs), numerical simulation, bottom gate top contact (BGTC), bottom gate bottom contact (BGBC), top gate top contact (TGTC)

Cite this Article

S.K. Jain, Shubham Dadhich, A.D.D. Dwivedi. Numerical Simulation based Comparative Study of P3HT based Top Contact and Bottom Contact OTFTs. Journal of Electronic Design Technology. 2019; 10(3): 27–32p.

Author Biography

  • Arun Dev Dhar Dwivedi, Department of Electrical and Electronics Engineering, Poornima University Jaipur
    Arun Dev Dhar Dwivedi has received the M.Sc. degree in Physics (Electronics) from BHU, Varanasi, India in 2003 and Ph.D. degree in Electronics Engineering from IIT (BHU) Varanasi, in 2010. He is currently working as Professor in Electrical and Electronics Engineering, Poornima University Jaipur. He Worked as a Visiting Scientist in Nanoelectronic group at the Laboratory IMS-CNRS-UMR5218, University of Bordeaux, Talence, France during 2014-2015. He also worked as senior Device modeling Engineer in Spice modeling division of  Silvaco Singapore office and as an Assistant Professor at Central University of Rajasthan and Central university of Jharkhand. He has given several invited talks in India and abroad at international meetings. He also worked as SRF and JRF at centre for research in microelectronics, IIT BHU Varanasi.  He is senior member of IEEE and Branch counselor IEEE students branch Poornima University Jaipur. He is in Editorial board member of International Journal of Advanced Applied Physics Research (IJAAPR), International Journal of Electrical Communication Engineering (IJECE), International Journal of Microelectronics and Digital Integrated Circuits (IJMDIC), International Journal of Analogue Integrated Circuits (IJAIC), International Journals of Power Electronics Controllers and Converters (IJPECC). He has been awarded by Early Career Researchaward from science and engineering research board (SERB) Department of Science and Technology (DST) Government of India and research grant of 50 lacks has been approved for his project entitled " Numerical simulation and compact modeling of organic thin film transistors for future flexible electronics". He has published more than 25 papers in international Journals and 25 papers in conference/seminars. He is reviewer of various international journals like IEEE transaction on electron devices, Organic electronics, journal of electronic materials etc.

    His research interest includes Microelectronics and VLSI design, Optoelectronics and Optical communication, Organic electronics, Semiconductor device Physics, Nanoelectronics, Technology Computer Aided Design (TCAD), EDA, Compact device modeling for IC design, Analog and Digital Integrated circuits and Infrared photodetectors.

     

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Published

2020-01-28

Issue

Vol. 10 No. 3 (2019)

Section

RESEARCH ARTICLES