Virtual Fabrication and Analog Performance of Sub-40nm Bulk MOSFET

Abstract

Virtual Fabrication of sub-40nm Bulk MOSFET  is carried out under channel engineering and source drain engineering process. These structures enable more aggressive device scaling in nano-scale region because of their ability to control short channel effects. How ever during scaling the junction depth should also be scaled down, which increases parasitic resistance so silicidation technique has been applied to reduce their effects on device. Analog performance has been measured in terms of gm, gds ,Av ,f_T and f_max .The simulation result predict that g_m is 3.75ms for engineered MOSFET as compared to non-engineered MOSFET with g_m of 2.9ms for similar gate length, similarly A_v for engineered device is 17.5db and for non-engineered device is 6.96db,f_T is 146GHz and for non-engineered f_T is 65GHz,f_max is 299GHz for engineered device and for non-engineered device f_maxis 170GHz and a comparison of an engineered device is done with a non engineered device to investigate the improved performance of an engineered device as compared to a non engineered device. Silvaco TCAD Tool is used for Virtual fabrication and simulation. ATHENA process simulator is used for virtual fabrication and ATLAS device simulator is used for device characterization.