1-Bit Full Adder's Analysis and Comparison

Authors

  • ankush chunn Department of VLSI Design, Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, Punjab, 144011 India
  • Vijay Kumar Sherawat Ajay Kumar Garg Engineering College, Ghaziabad, 201009 India

DOI:

https://doi.org/10.37591/joedt.v6i2.4941

Abstract

The full adder circuit forms the basis of majority of digital circuits. Improvement in a basic full adder circuit in terms of area, power and delay affect the performance of whole system. It becomes compulsory to investigate and analyze the performance of implementation of full adder circuit in literature, till now. In this paper, a study is carried out to look into performance parameters of full adder circuit using different logic styles. The simulations are carried out on SPICE using 0.25 um technology.

Keywords- CMOS Circuit, VLSI, Full adder, Adder

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Published

2021-01-13

Issue

Vol. 6 No. 2 (2015)

Section

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