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Detection of Fault and Protection of Faulted Distribution Feeder with Field Programmable Gate Array Using State Diagrams

Arindam Biswas, Sujit Dhar, Ashoke Kumar Basu, Amarnath Sanyal

Abstract


A hardware-efficient algorithm for fast fault-detection in feeders radiating out of a distribution substation and its subsequent clearance from the system for safe operation of the healthy parts has been presented in the paper. State diagrams used to design the circuit.The general purpose SPARTANE 3AN FPGA kit has been employed for developing the protective over-current relay. All the coding has been done using the hardware description language VERILOG. To avoid malfunctioning due to transient over-currents, a delay-logic has been used for built-in relay operation. The performance of the proposed scheme has been evaluated through case-studies on a hypothetical 11 kV bus-feeders of a 132/66/33/11 kV substation. The experimental results on fault currents converted to digital voltage signals show that the hardware scheme is feasible for all practical applications

Keywords


Field programmable gate array (FPGA), state diagram, sub-station, fault detection, over-current delay

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References


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DOI: https://doi.org/10.37591/jomea.v2i2.5270

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