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A Novel Architecture of Control System Processor Using Field Programmable Gate Array

Arindam Biswas, Amitabha Sinha


This paper presents a reconfigurable architecture of control system processor. The performance of the proposed architecture has been evaluated by taking different controllers and phase lead and phase lag networks. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty of the architecture for control system. This paper investigates the potential use of FPGAs for implementing efficient “Reconfigurable Processor” for control system applications. The proposed processor is based on parallel re-configurable which is implemented on FPGA. FPGAs have become an important component for implementing these functions with respect to cost, performance and flexibility. The general purpose SPARTAN 3AN FPGA kit has been employed for developing reconfigurable processor, with all the coding done using the hardware description language VERILOG.


Field programmable gate array (FPGA), reconfigurable architecture, digital signal processor (DSP), application specific integrated circuit (ASIC), basic building block (BBU), functional unit (FU), system on chip (SOC), configurable logic block (CLB), look

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