Analysis of DIBL Effect in MOSFET Working

Abstract

Abstract

One of the most widely used electronic devices, particularly in digital integrated circuits, is the metal insulator semiconductor (MIS) transistor. Most of the existing transistors used in fabrication of integrated chips are with junctions. The device scaling is growing the channel length between junctions in devices are scaling gone down to 10 nm. Drain Induced Barrier Lowering (DIBL) effect is prominent as the feature size of MOS device keep diminishing. In this paper, a threshold voltage model for small-scaled strained Si n channel MOSFET is proposed to illustrate the DIBL effect. A MOSFET device is taken into account to be short once the channel length is that the same order of magnitude because the depletion-layer widths (x_dD, x_dS) of the supply and drain junction. As the channel length L is reduced to extend each the operation speed and the number of element per chip, the alleged short-channel effects arise. The model used shows however the DG-MOSFET parameters like the semiconductor thickness, compound thickness, drain bias, and channel length, have an effect on the blink voltage degradation.

Keywords: MOSFET, DBIL, short Channel, Threshold voltage

Cite this Article

Pankaj Batra. Analysis of DIBL Effect in MOSFET Working. Journal of Microelectronics and Solid State Devices. 2018; 5(3): 33–40p.