A Novel Register Minimization Technique for Efficient Implementation of BLMS Filter

Abstract

Purpose: This paper presents a novel register minimization technique for the BLMS filter. The purpose is to reduce the number of registers leading to reduction in hardware resource used for BLMS filter and thus reducing the complexity. Design/Methodology/Approach: In the BLMS filter due to substantial number of register and hardware resource, Strassen’s algorithms are used to minimize the registers. Strassen’s algorithm is used for the matrix multiplication in the BLMS filter for the minimization of register. System Verilog code were written for this followed by synthesis in RC tool (VIVADO). LUT, DSP and IO reports were subsequently generated and RTL schematics were also obtained for this algorithm. This algorithm leads to reduction in the number of multipliers which is described in this paper. Findings: Apart from the reduction in the number of multipliers a corresponding reduction in the LUT, DSP and IO were also obtained. A substantial decrease in the number of multiplier which is seven now, LUT utilization reduced to 44.82%, DSP utilization 124.44% and IO is 996%. Originality/Value: This paper presents an approach for register minimization which ultimately leads to reduction in its hardware resource and iteration period. This is achieved by reducing the multiplier count which accounts for a large portion of registers. The proposed methodology has been described in context of the matrix multiplication for the first time. The main advantage of this algorithm is that it reduces the number of registers hence the hardware complexity is also reduced