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Investigation of Pass Transistor Logic and CMOS Logic Configuration Based D-Multiplexers

Srinivas Dharavath


Pass Transistor Logic (PTL) arrangement depicts a few rationale families utilized in the plan of incorporated circuits. It lessens the include of transistors utilized making distinctive rationale entryways, by killing excess transistors. The pass transistor is driven by an intermittent clock flag and goes about as an entrance change to ON (1) or OFF (0), contingent upon the information flag. The utilization of pass transistor    rationale has brought about noteworthy enhancement in the execution of de- multiplexer structures utilized for rapid processing. The execution of a De-Multiplexer using Pass Transistor Logic Configuration (PTLC) and CMOS Logic Configuration is investigated in this examination paper (CLC).Furthermore, a correlation between the exhibitions of both the setups as far as power and region. Other than this, paper additionally implies over half decrement in zone and number of transistors check while utilizing pass transistor rationale design in contrast with de- multiplexer executed with CMOS rationale arrangement. In addition, decrease in power dissemination up to 70% is seen in pass transistor rationale contrasting with CMOS rationale.


CMOS design, De-multiplexer, Pass transistor , Power dispersal, Chip region

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