Study of Cascaded H Bridge Multilevel Inverter

Authors

  • H. Patel Department of Electrical Engineering, G. H. Patel College of Engineering and Technology, V.V. Nagar, Gujarat, India
  • C.V. Sheth Department of Electrical Engineering, G. H. Patel College of Engineering and Technology, V.V. Nagar, Gujarat, India

DOI:

https://doi.org/10.37591/.v6i1.1609

Abstract

The inverters are now-a-days used broadly. Inverters are classified as two level inverters and multilevel inverters. There are too many limitations; conventional inverters at high power and high voltage applications. So, multilevel inverters become useful for high power and high voltage applications due to their increased number of levels at the output voltage. The harmonics are reduced by increasing the number of levels and output voltage has a tendency to-end-up more unadulterated i.e., sinusoidal. Multilevel inverter have three sorts of topologies like; first one is DCMLI (Diode clamped multilevel inverter), second one is FCMLI (Flying capacitor multilevel inverter) and third one is CHBMLI (Cascaded H-bridge multilevel Inverter). CHBMLI is a promising topology when compared to the other topologies. It reaches to higher output voltage and power levels for which the reliability is higher due to its modular topology and simplicity. The imperative element of multilevel inverter is total harmonic distortion. This paper analyzes the THD in 5, 7 and 9 levels of cascaded H-bridge multilevel inverter utilizing SPWM control technique. For worthy control in the yield voltage of inverter SPWM control procedure is utilized, as a part of the terminating circuit. The analysis has been simulated using MATLAB/SIMULINK technique.

 

Keywords: Multilevel inverter, diode clamped MLI, fly capacitor MLI, cascaded H Bridge MLI, total harmonic distortion

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Published

2019-02-15

Issue

Vol. 6 No. 1 (2016)

Section

Research Article

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