Implementation and Analysis of Full Adder using low Power Adiabatic Techniques

Abstract

Abstract

In this study, authors have discussed, designed and compared the low power adiabatic logic energy efficient recovery logic (ECRL) and positive feedback of adiabatic logic (PFAL) with conventional Complementary Mosfet (CMOS) logic. A one-bit full adder using these design techniques are implemented and results are compared like power, delay, transistor count and power delay product. Tanner tool v13 is used for designing of schematic and simulation. From the result, it is found that PFAL technique is better as compared to ECRL in terms of stability but the transistor count and average power of PFAL is more as compare to ECRL.

Keywords: adiabatic, CMOS logic, energy efficient recovery logic, full adder, low power, positive feedback of adiabatic logic

Cite this Article

Nidhi Vashist, Sambhavi. Implementation and Analysis of Full Adder using low Power Adiabatic Techniques. Journal of Semiconductor Devices and Circuits. 2018; 5(2): 1–8p.