An Optimized 32 bit Carry Select Adder Using Modified BEC

Abstract

Abstract

Adders play a major role in addition of numbers, multiplications and other advanced processors’ design. Among the conventional adder structures, carry select adder is known to be fastest adder. This adder circuit is used for the design of high speed processors. The CSLA adder architecture is such that it is of less power dissipation, area efficient and high speed. CSLA circuit for 8, 16, 32 bits is designed without multiplexer and parameters like area, power and delay are compared with that of existing system. In this paper, parameters like area, power and delay of the design work are compared with the regular CSLA adder and implemented in Cadence Virtuoso tool. The results show that CSLA using modified BEC is more efficient than the conventional CSLA in terms of area, power and delay. 

Keywords: Carry select adder, CMOS, cadence virtuoso, XNOR, binary to excess one converter

Cite this Article

Jeril Joseph, Gopakumar MG. An Optimized 32 bit Carry Select Adder Using Modified BEC. Journal of Semiconductor Devices and Circuits. 2018; 5(2): 27–32p.