Digital Front-End Architecture of ECG Acquisition System with 0.5V Supply

Abstract

Abstract

Due to the popularity of portable electronic products, low power systems have attracted more attention in recent years. Dynamic power consumption remains to be the biggest contributor to the total power consumption of a hardware design. A new power efficient electrocardiogram acquisition system that uses a fully digital architecture to reduce the power consumption and chip area has been proposed in this paper. The design of analog-to-digital converters (ADCs) is based on digital delay lines. Instead of analog block, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. A moving average voltage-to time converter is used, which behave instead of the LNA and antialiasing filter. A digital feedback loop is employed to cancel the impact of the dc offset on the circuit, which eliminates the need for coupling capacitors. The simulation results show that the front end of the circuit consumes 274 nW of power.

Keywords: Digital integrated circuit (IC), electrocardiogram (ECG), low power, moving average filtering, offset cancellation

Cite this Article

Aswathy BS, Finolina EstherP. Digital Front-End Architecture of ECG Acquisition System with 0.5V Supply. Journal of Semiconductor Devices and Circuits. 2016; 3(2): 11–20p.