Performance Analysis of Bootstrapping Techniques to Overcome the Threshold Voltage Drop in NMOS Logic Design

Abstract

Abstract: In this paper, we study the concept of bootstrapping techniques and analyzed its performance in digital CMOS circuits. These bootstrapping circuits are used to increase the gate voltage of transistors so that drain node voltage can be pulled high to overcome the threshold voltage drop problem in NMOS logic design. Also discuss the drawback associated with voltage bootstrapping techniques in NMOS logic design that is sneak path problem between supply voltage and ground. This work has been simulated on Pyxis schematics tool of mentor graphics using TSMC018 CMOS process technology.

Keywords: Voltage Bootstrap capacitance, NMOS logic circuits, output swing, VLSI

Cite this Article

Mangal Deep Gupta, B.P. Panday, R.K. Chauhan. Performance Analysis of Bootstrapping Techniques to Overcome the Threshold Voltage Drop in NMOS Logic Design. Journal of Semiconductor Devices and Circuits 2019; 6(1): 15–20p.