Design and Implementation of Array for Scaling Power and Area in 4t SRAM Cell

Abstract

In this article in order to reduce the power and area of the Static Random-Access Memory (SRAM) array while maintaining the competitive performance. By using the CMOS technology, the design structure is made to for desired configuration of SRAM array by utilizing the SRAM cell and six-transistor (6T), In order to reduce the number of switches for enhancing performance working with the deep submicron of values 130nm, 90nm and 65nm is achieved using the CMOS technology. Except the pre charge circuits and the basic storage cells, remaining part of the circuitry is same for both 6T SRAM array and New Load less 4T SRAM array. Compared to the conventional 6T SRAM array, the new load less 4T SRAM array consumes less power with less area in deep submicron CMOS technologies. Also, the SNM of the new load less 4T SRAM cell is as good as that of the 6T SRAM cell for higher values of Cell Ratio (CR), The simulation and verification are made using H-spice tool and analysing the reduction parameters such as, reduced power dissipation, noise ratio, reduced size and processing time.