FPGA Implementation of Variable Step Size Adaptive Filters for Signal De-noising

Authors

  • Ravi Kumar Department of Electronics & Communication Engineering Thapar University, Patiala, 147004, Punjab, India
  • Aditya Bali Department of Electronics & Communication Engineering Thapar University, Patiala, 147004, Punjab, India

Abstract

This paper presents the design and implementation of a variable step size 40 order adaptive filter for de-noising acoustic signals. Four different adaptive filters (LMS, Sign-Data, Sign-Error and Sign-Sign) were designed using three different structures, viz., direct form, transposed and the proposed structure and their de-nosing performance was compared. Further, the filters were implemented on three different Field programmable gate arrays (FPGAs), viz., Spartan 6, Virtex 6 and Viretx 7 which are designed on three device families and their speed , power and area utilization are computed. It was observed that due to significant reduction in the critical path, the proposed structure uses less number of slice LUTs resulting in a reduction in silicon area without incurring any significant overhead in terms of power or delay.

Keywords: adaptive filters, field-programmable gate array (FPGA), hardware description languages (HDLs), high-level synthesis (HLS), least means square (LMS), de-noising

Published

2015-12-03

Issue

Vol. 1 No. 1 (2015)

Section

Research Articles