Suitability of Various Low Power Strategies for SRAM Design: A Survey

Authors

  • Balwinder Singh LAKHA Senior Engineer, Centre for Development of Advanced Computing, Mohali, Punjab, India
  • Hitesh Pahuja Research Scholar , Desh Bhagat University, Mandi Gobindgarh, Punjab, India.
  • Sudhakar Panday Assistant Professor, Desh Bhagat University, Mandi Gobindgarh, Punjab, India

Abstract

In very high performance system on chip, static power dissipation plays a dominant role compared to dynamic component and it increases with technology scaling. Scaling of bulk MOSFET faces more and more challenges at 45 nm technology or below by producing short channel effect (SCE) which leads to increase in leakage current. An obstacle with bulk MOSFET at 45 nm or below gate length includes SCE, subthreshold leakage and gate dielectric leakage. Nowadays, bulk CMOS technology is going to replace by most promising FinFET technology. In this paper, a survey on latest techniques has been proposed related to both industrial and academic domain to minimize the leakage power, SCE, delay and area in SRAMs. The surveyed analysis cover a range from device selection, geometry, process variation to circuit level techniques suitable for various low power SRAM design.

Keywords: CMOS, FinFET, MOSFET, system on chip, SCE

Cite this Article:Pahuja H, Panday S, Singh B. Suitability of Various Low Power Strategies for SRAM Design: A Survey. Journal of Semiconductor Devices and Circuits. 2015; 2(1): 6–13p.

Published

2015-12-03

Issue

Vol. 1 No. 2 (2015)

Section

Research Articles