Design of a 10-bit Segmented Current-Steering CMOS D/A Converter for High Speed Communication System

Authors

  • Anil K. Saini IC Design Group, CSIR-Central Electronics Engineering Research Institute, Pilani, Raj-333031, India
  • sanjay singh

DOI:

https://doi.org/10.37591/jovdtt.v2i1-2-3.2946

Abstract

In the present work, design of a 10-bit digital-to-analog (D/A) converter using current segmentation architecture in 0.35 µm double-poly, four-metal, CMOS process has been attempted. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.8 and 2.5 least significant bits (LSBs) respectively. For sampling frequency of 12-MSample/s, the spurious free dynamic range (SFDR) is better than 56 dB for signal up to Nyquist rate. The worst case power consumption is 58 mW and it operates with a single supply voltage of 3.3.

 

Keywords: Digital-to-analog converters, binary weighted, matching, current-steering, CMOS

Downloads

Published

2019-08-08

Issue

Vol. 2 No. 1-2-3 (2012)

Section

Articles

License

Thank you for submitting the manuscript to the Journal of VLSI Design Tools & Technology. With the online journal management system that we are using, you will be able to track its progress through the editorial process by logging in to the journal web site:

An author may request for withdrawal of his/her manuscript, within a week's
time  (w.e.f. the date of submission of the manuscript). The Author is
recommended to follow strictly the Instructions in Manuscript Withdrawal
Policy (As per URL given below)
http://stmjournals.com/pdf/manuscript%20withdrawl.pdf


If you have any questions, please contact me. Thank you for considering this
journal as a venue for your work.