Low Power RF QPSK MODEM Design

Abstract

System-level simulation including design of CMOS circuits for radio frequency QPSK MODEM targeting applications in 2.45 GHz industrial, scientific and medical (ISM) band has been presented in this paper. Based on the QPSK architecture, the MODEM consists of an analog mixer using a voltage multiplier, a 90 °phase shifter, delay circuits, a voltage adder and a filter to detect the information. A code reuse subsystem block consisting of Chebyshev filter type-II and lowpass RC filters is used prior to determine the envelope of the signal. The design will be useful in analog signal processing for its monolithic integration having higher speed and low cost. The MODEM circuit has been designed using SCL 1.2 µm CMOS foundry’s model parameters. It can operate at a supply voltage of 3.5 V. The circuit consumes power less than 3.5 mW and analog mixer performs a conversion gain of + 9.54 dB (< 10 dB). Simulink system-level simulation verifies the stepwise behavioral aspects of the QPSK architecture and proves that its CMOS circuit’s design presented in the paper shows similarity in the behavior with acceptable performance loss with respect to ideal case.

Keywords: QPSK RF MODEM, analog CMOS circuit design, phase shifter, envelope detector, filter