Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-simulation

Authors

  • akash mecwan Department of Electronics and Communication, Institute of Technology, Nirma University, Ahmedabad, Gujarat, India
  • bhupendra fataniya
  • dhaval shah

DOI:

https://doi.org/10.37591/jovdtt.v6i1.2971

Abstract

Image processing is one of the most booming research areas in modern days. Every modern device incorporates image processing in one or the other way. Most of the image processing algorithms start with basic edge detection. The performance of the edge detection can be improved using state of art FPGA devices. Implementation using field programmable gate arrays (FPGA) speeds up the processing of edge detection algorithms. The paper discusses the implementation of edge detection algorithm on Virtex 5 series of FPGA. The design is implemented in Xilinx System Generator using MATLAB and the simulation is performed using Hardware Software Co-simulation. The output of implementation is observed in MATLAB environment. The algorithm is tested for file as well as real-time images.

 

Keywords: FPGA, edge detection, hardware software co-simulation

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Published

2019-08-09

Issue

Vol. 6 No. 1 (2016)

Section

Articles

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