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Low-Offset High Speed CMOS Voltage Comparator using 180 nm Technology

Rohitkumar M. Joshi, priyesh p gandhi


A low Off-Set high-speed two-stage dynamic comparator is presented in this paper. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18 µm CMOS technology prove that the proposed circuit reduces the power consumption by a factor of two and reduces comparison time as large as 210ps in the same budget of offset voltage compared to the conventional circuit. Moreover, the offset voltage and power consumption of the comparator trades with the speed which is simply controlled by the delay of the second stage. As a result, a low-power comparator for given offset and speed requirements can be designed efficiently. This comparator generated off–Set voltage is 2 mV and power consumption is 190 µW.


Keywords: Dynamic comparator, Low Off-set comparator, High-speed comparator, Delayed comparator

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