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Low Power High Speed Eight-Transistor (8T) SRAM Cell with Enhanced Data Stability

P. Raikwal, V Neema, A Verma


The demand of static random access memory cell in embedded memories is rapidly increasing. To design SRAM is continuously becoming difficult due to limitation of weaker write margin, degraded data stability and higher leakage power consumption. In order to overcome these limitations, new 8T SRAM has been explored. The simulation results depicts better data stability, low access delay and decreased leakage power consumption. Alternatively, proposed cell with sleep transistor and cell with dual threshold voltage (DVT) is designed, also. The evaluated parameters of all the circuits are compared with conventional 6T SRAM cell. When comparison of the different parameters carried out, the new 8T SRAM cell shows the data stability is increased up to 47.5% and 33.7% during read operation and hold state respectively as compare to conventional 6T SRAM cell. The results depict, read and write access delay is deducted up to 27.9x and 55.6x respectively when compared with 6T SRAM cell. Additionally, the new 8T SRAM circuit with DVT consumes 2.842pA leakage current, which is 92.05% less than 6T SRAM cell.


Keywords: SRAM, DVT, data stability, write margin

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eISSN: 2249–474X