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Single Bit Low-Power High-Speed Full Adder

Sachin Pandurang Gaikwad, Sujatha kondakinda, Harsh Upadhyay


This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then extended it for 32 bit also. The circuit is implemented using Tanner EDA tools in 125 nm technology. The circuit parameters such as power, delay, and layout area were compared with the technology and compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. In comparison with the existing full adder designs, the present implementations were more significant improvement in terms of power and speed.


Index Terms: Carry propagation adder, high speed, hybrid design, low power


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