Hierarchical Methodology Approach to SOC Design: A Comprehensive Look

Abstract

The design scale of a chip has increased many folds in the last few years and shows a continuous exponential trend. This is made possible by the reduction in transistor size and an evolving process technology. As a result, it is possible to move to SoC technology (System on Chip-A single die consisting of multiple subsystems) rather than a traditional ASIC. This has obviously resulted in an increase in the instance/gate count and the functionality of the chip resulting in a multi core subsystems based designs. Hence software scalability is needed to support the increasing complexity in the function of the chip and the related timing analysis and operations based on it. Originally for small ASICS flat implementation was sufficient and was most accurate. For SoC’s it is replaced with a modular approach in handling designs which is now is further improved for accuracy using the concept of Interface Models that have various degrees of edit ability and accompanying flows. This paper starts with flat description ‘of flow implementation traditionally used by EDA tool companies and then go on to comprehensively describes hierarchical implementation flows and their artifacts like, models, post assembly ECO, context views, feasibility flows among others. We are also going to look at advances in the tool technology of timing graph reduction and physical data reduction that enables new flow implementations and can be applied to both hierarchical and flat methodologies.