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Impact of Work Function Variations on Data Stability of FinFET based 6T SRAM Cell

Mitesh Limachia, Rajesh Thakker, Nikhil Kothari

Abstract


The performance of FinFET SRAM cell is severely affected due to metal gate work function variations (WFV) in FinFET device. In order to provide guidelines for SRAM cell optimization, it is essential to examine the data stability due to the contribution of each cell transistor from WFV point of view. In this work, we investigate the effect of VTH variations of each transistor of tri-gated FinFET 6T SRAM cell on stability parameters (WSNM and RSNM) in 20 nm technology at VDD 0.9 V to examine the overall data stability under the influence of each transistor’s WFV, which has a strong relation with number of fins. Simulation results reveal that VTH and subsequently, VTH variations of PD transistors and PG transistors have severe impact on σWSNM, which is minimized by using more number of fins in PD and PG transistors. This, in turn, helps to secure write operation stability and reduces number of write failures. The strength of correlation between the VTH of cell transistor and RSNM indicate that PDL and PUL variations correlate to SNML, and the PGL and PDL variations correlate to the SNMR. The trade-off is observed between VTH of PDL and RSNM.


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S.H. Rasouli, H. Koike, and K. Banerjee. High-speed low-power FinFET based domino logic, Design Automation Conference; 2009 Jan 19-22; Yokohama, Japan, US:ASP-IEE 2009.829-834 p.

Joyoung Song, Yu Yuan, Bo Yu, et al. Compact Modeling of Experimental n- and p-Channel FinFETs. IEEE Transactions on Electron Devices. 2005;.57(6):1369-1374.

Chih-Hong Hwang, Yiming Li, Ming-Hung Han. Statistical variability in FinFET devices with intrinsic parameter fluctuations. Microelectronics Reliability. 2010; 50(5): 635–638.

V.S. Basker, T. Standaert, H. Kawasaki, et al. A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch, VLSI Symp. Tech. Dig;2010 June 15-17; Honolulu, HI, USA. New Jersey, United States.2010.19–20.

D. Bhattacharya and Niraj. Jha. FinFETs: From devices to architectures. Advances in Electronics, Hindawi Publishing Cooperation.2014, 2014: 1-21.

Mitesh Limachia, Dixit Vyas, Rajesh Thakker, et al. Hybrid Offset Compensated Latch-Type Sense Amplifier for Tri-Gated FinFET Technology, in INTEGRATION, the VLSI Journal of Elsevier.2018; 62:258-269.

Jean-Pierre Colinge. Multiple-gate SOI MOSFETs. Solid-State Electronics. 2004; Elsevier. 48: 897–905.

Mitesh Limachia, Rajesh Thakker, Nikhil Kothari, A Near-threshold 10T Differential SRAM Cell with High Read and Write Margins for Tri-Gated FinFET Technology in the INTEGRATION. the VLSI Journal of Elsevier,2017;61(c):125-137.

M.L. Fan, V.P.H. Hu, Y.N. Chen, P. Su, C.T. Chuang, “Variability analysis of sense amplifier for FinFET subthreshold SRAM applications,” IEEE Trans. Circuits Syst. II Exp. Briefs. 2012; 59(12), 1031–1035.

Seid Hadi Rasouli, Kazuhiko Endo and Kaustav Banerjee, Variability Analysis of FinFET-Based Devices and Circuits Considering Electrical Confinement and Width Quantization. ICCAD. 2009; 2009: 505-512.

Kazuhiko Endo, Shinichi O’uchi, Member, IEEE, Yuki Ishikawa, et al. A Correlative Analysis Between Characteristics of FinFETs and SRAM Performance. IEEE Transactions on Electron Devices.2012;59(5):1345-1452.

Toshiro Hiramoto, Makoto Suzuki, Ken Shimizu, et al. Direct Measurement of Correlation Between SRAM Noise Margin and Individual Cell Transistor Variability by Using Device Matrix Array. IEEE Transactions on Electron Devices.2011;58(8) :2249-2256.

O. Hirabayashi, A. Kawasumi, A. Suzuki, Y, et al. A process-variation-tolerant dual-power supply SRAM with 0.179 μm2 cell in 40 nm CMOS using level programmable wordline driver in Proc. ISSCC Dig. Tech. Papers; 2009 Feb 8-12; San Francisco, CA, USA. New Jersey, United States: IEEE;2009. 458–459 p.

B. Doyle, B. Boyanov, S.Datta,M. Doczy, et al. Tri-gate fully-depleted CMOS transistors: Fabrication, design and layout. in Proc. IEEE Symp. VLSI Technol. Dig. Tech. Papers, 2003 June 10-12; Kyoto, Japan. New Jersey, United States: IEEE;2003. 133–134 p.

Rajesh A. Thakker, Mayank Srivastava, Ketankumar H. Tailor, et al. A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs; Microelectronics Journal.2011; 42(5).

C. Meinhardt, A. L. Zimpeck and R. A. L. Reis, “Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations,” Microelectronics Reliability. 2014; 2014:2319–2324.

Hui-Wen Cheng. Metal-Gate Work-Function Fluctuation in 16-nm Single-and Multi-fin Field Effect Transistors with differenent aspect ratio in proceddings of ICSE2010 Proc; 2010 June 28-30; Malacca, Malaysia: IEEE;2010.48-51 p.

Hamed F. Dadgour, Kazuhiko Endo, Vivek K. De, et al. Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors: Modeling, Analysis, and Experimental Validation. IEEE Transactions on Electron Devices.2010; 57(10): 2504-2514.

Andrew Carlson, Zheng Guo, Sriram Balasubramanian, et al. SRAM Read/Write Margin Enhancements Using FinFETs. IEEE Transactions on very large scale integration (VLSI) systems.2009;18(6):1-14.

PTM, Predictive Technology Model (2011, Jan). [online]. Available from http://ptm.asu.edu/.


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