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A Nobel Approach of Designing A 4 Bit Carry Skip Adder Using Reversible Logic

Pinaki Satpathy, Santanu Maity


This paper presents a method to designing Various Adder Circuits using CMOS Logic Style for Energy-Efficient Arithmetic Applications. We present Ripple Carry Adder, Carry Bypass Adder, Carry Look Ahead Adder and Carry Skip Adder in CMOS logic styles that lead to have reduced power-delay product (PDP). We executes a comparison against each other adders which finally provide result as having a low PDP, with reference to power consumption, speed and area. All the full-adders were constructed with a 90 um CMOS technology, and were basically examine using a comprehensive test bench that allowed quantify the current taken from the full-adder inputs, besides the current provided from the power supply. Post-layout simulations show that the proposed full-adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area.

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Sung Mo-Kang, Yusuf Leblebici. CMOS Digital Integrated Circuits-Analysis and Design. Third Edition. Mc Graw Hill; 2010.

Guide to the Tanner EDA for VLSI. (1988) Montana State University [Online]. Available from [Accessed 2005]

L. Bisdounis, D. Gouvetas, and O. Koufopavlou., “A Comparative study of CMOS circuit design styles for Low Power high Speed VLSI circuits”. International Journal of Electronics. 1998; 84 (6): 599–613.

YannisTsividis. Operation and Modelling of the MOS Transistor. second edition, Oxford publication, 2010.

J.W. Bruce, M.A. Thornton, L. Shivakumaraiah, P.S. Kokate, X.Li, “Efficient Adder Circuits Based on a conservative Reversible Logic Gate”. Proceedings IEEE Computer Society Annual Symposium On VLSI. New Paradigms for VLSI Systems Design, ISVLSI 2002, 25–26 April 2002 Pittsburgh, PA, USA. US: IEEE; 2002. 83–88p.

F. Najm. “A survey of power estimation techniques in VLSI circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1994; 2 (4): 446–455.

S.M. Kang. “Accurate Simulation of Power dissipation in VLSI circuits”. IEEE Journal of Solid State Circuits. 1986; 21 (5): 889–891.

P. Satpathy. ‘Implementation of Carry Select adder with Reduced Area Scheme’. Journal of VLSI Design Tools & Technology. March 2017.07 (1): 1–5.

I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin and Chien-Chang Peng, “An area-efficient carry select adder design by sharing the common boolean logic term” Proceedings of the International Multiconference of Engineers and Computer Scientists IMECS. March 14–16, 2012; Hong Kong. Microsoft Word; Vol. II.


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