A Reliable Low Standby Power 6T SRAM Cell

Abstract

The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell uses a robust cross-coupled design that combines a Schmitt-trigger inverter with a double-length pull-up transistor and a regular inverter with a stacking transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the true internal storage nodes, effectively eliminating read-disturbance issues. This distinction guarantees that the read operation won't will not affect the data that has been stored. In terms of write operation, the LP10T SRAM cell employs a pseudo-differential approach using a write bitline and control signal, supplemented by a write-assist technique. This configuration enhances the write-ability of the cell. To evaluate the performance of the proposed LP10T SRAM cell, it is compared with several state-of-the-art SRAM cells using the Mentor Graphics tool in a 16-nm CMOS predictive technology model. The evaluation is conducted under harsh manufacturing process conditions, including variations in voltage and temperature, with a supply voltage of 0.8 8 V. The LP10T SRAM cell demonstrates favourable performance metrics compared to the other SRAM cells. It achieves the third-best read dynamic power and the second-best write dynamic power, with power reductions of 29.69% and 26.87%, respectively, in comparison to the standard 6T SRAM cell. Furthermore, the LP10T SRAM cell minimizes leakage power consumption through its design. It exhibits a leakage power reduction of 37.35% compared to the 6T SRAM cell and a 12.08% reduction compared to the best-studied cells. Overall, the proposed LP10T SRAM cell offers improved read stability and write-ability while significantly reducing power consumption, making it a promising choice for low-power and high-performance SRAM applications.