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Exploring the Potential of Adiabatic Logic for Low Power Nano-scale VLSI Designs
Abstract
Low power dissipation has emerged as one of the main research areas due to the ongoing scaling down of device technology in the area of VLSI circuit design. Adiabatic logic gates are a practical answer to the rising demand for low power portable gadgets. Various adiabatic logic families, including 2N-2N2P, PFAL (Positive Feedback Adiabatic Logic), DCPAL (Differential Cascode and Pre-resolved Adiabatic Logic), and a suggested circuit centred on the PFAL logic circuit in CMOS, FinFET, and CNTFET technology, are presented in this work. This study examines various adiabatic logic families, including ECRL, 2N-2N2P, and PFAL. The proposed design saves up to 70% of average power and 50% of delay in CNTFET technology, according to all simulations performed using HSPICE at 16 nm technology with a supply voltage of 0.9 V and a frequency range of 10 MHz to 1 GHz. It can be seen that proposed DCDB-PFAL logic exhibits significantly lower power dissipation than other adiabatic logic families by comparing the performance of proposed adiabatic logic circuits to that of other adiabatic logic families.
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References
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