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Optimization and Analysis of InGaAs Vertical Nanowire Transistor for Memory Array Applications
Abstract
In this paper, we present a cylindrical gate all around In 0.53 Ga 0.47 As Vertical Nanowire Transistor (VNWT) on silicon at ultra-short
channel gate length 14nm by numerical simulation approach. The In 0.53 Ga 0.47 As VNWT device dimensions like diameter, source and drain
extension length and channel doping are taken as critical process parameters and optimized for better performance. The proposed device is
scalable up-to 10nm with a maximum On-current of 5.6mA, leakage current of 2nA and I on /I off ratio up to 10 6 . The ac characteristics of the
proposed In 0.53 Ga 0.47 As VNWT is analyzed for various gate voltages and gate to source capacitance, gate to drain capacitance and
transconductance are obtained. The device can operate at a cut off frequency of 6 GHz and a maximum operating frequency up to 9.8GHz. A 3x1,
5x1 cross bar memory layout arrangement and a 3x3 memory array are built using In 0.53 Ga 0.47 As VNWT devices. In 5x1 array arrangement InGaAs
VNWT shows 44% better I on /I disturb ratio than horizontal HNWT devices. The VNWT device can be used as a memory element in high frequency,
low power applications.
Keywords
References
KaushikNayak, Mohit Bajaj, Aniruddha Konar.et.al and V.RamgopalRao, " Negative differential conductivity and carrier heating in
gate-all-around Si Nanowire FETs and its impact on CMOS logic circuits", Japanese Journal of Applied Physics", Vol.53, pp-
EC16-1-7, February 2014.
G.Larrieu, X.L.Han, "Vertical Nanowire array based FETs for ultimate scaling", Nanoscale, Vol.5, pp-2437- 2441, January 2013,
Nanoscale, https://pubs.rsc.org/en/content/articlelanding/2013/NR/c3nr33738c.
Pierre Colson, Catherine Henrist, Rudi Cloots, “Nanosphere lithography: A powerful method for the controlled manufacturing of
Nanomaterials”, Journal of Nanomaterials, Vol.2013, https://doi.org/10.1155/2013/948510.
J.A.DelAlamo,D.H.Kim,"The prospects for 10nm III-V CMOS", IEEE International Symposium on VLSI-TSA, pp-166-167, April
, IEEE Xplore.
G.Atwood,”Future directions and challenges for ETox flash memory scaling”, Device and materials Reliability, IEEE transactions on,
vol.4, issue-3, pp. 301-305, September 2004, IEEE Xplore, https://ieeexplore.ieee.org/document/1369190.
Subha Subramaniam,Sangeeta.M.Joshi,R.N.Awale,”Suita bility of High-k Gate Dielectrics on the Device Performance and Scalability
of Nanoscale Double Gate FinFETs:Simulation Study ”, Journal of Electron Devices (JED), FRANCE, Vol.18, pp.1582-1586, 2013.
SubhaSubramaniam, Sangeeta.M.Joshi, R.N.Awale, ”Impact of Metal Gate Work Function in sub-22nm Double-Gate FinFETs with
SiO2 and High-k Gate Oxides: A Simulation Study”, International Conference on Electronics and Communication Systems
(ICECS'14), Coimbatore, IEEE Electron Device Society, pp-299- 303, 14th Feb 2014, IEEE Xplore.
Cogendapte Ltd,"Cogenda Genius Device Simulator User Guide",2011,
Schenk, A. “Finite-temperature full random-phase approximation model of band gap narrowing for silicon device simulation” ,Journal of
Applied Physics, Vol. 84(7), pp. 3684-6395, 1998, https://iis-people.ee.ethz.ch/~schenk/bgnTechRep.pdf
C. Lombardi, S. Manzini, A. Saporito and M. Vanzi, “A Physically Based Mobility Model for Numerical Simulation of Nonplanar
Devices”, IEEE Transaction Computer Aided Design, pp. 1154-1171, Vol. 7, 1992, IEEE Xplore.
H.R.Yeager, R.W.Dutton,’Circuit Simulation Model for the high electron mobility Transistor’, IEEE Transaction on Electron Devices, pp-
-692, 1986, Volume-33, issue-5, IEEE Xplore, https://ieeexplore.ieee.org/document/1485769.
T.K.Agarwal, O.Badami, S.Ganguly.et.al,"Design Optimization of Gate-All-Around Vertical Nanowire Transistors for Future Memory
Applications",EDSSC IEEE Conference, 03-05 th June-2013, China, IEEE Xplore, https://ieeexplore.ieee.org/document/6628113.
Youssouf Guerfi and Guilhem Larrieu, "Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate- All-Around", Nanoscale
Research Letters, 19 th -april-2016,Nano-scale research letters, Springer, DOI 10.1186/s11671-016-1396-7
J.J,Gu, X.W.Wang et.al,” III-V Gate-all-around Nanowire MOSFET Process Technology: From 3D to 4D”, Electron Device Meeting,
IEDM 2012, IEEE International 23.7, pp-1-23.7.4, 10-13 th - December-2012, San Francisco, U.S.A., IEEE Xplore,
https://ieeexplore.ieee.org/document/6479091
J.J.Gu et.al,”Size dependent study of In 0.53 Ga 0.47 As Gate-all-around Nanowire MOSFETs: Impact of Quantum Confinement and Volume
inversion”, IEEE Electron Device Letters.2012, Vol.33, July, 2012,pp-967-969,
https://engineering.purdue.edu/~yep/Papers/IEEE%20EDL_Volumn%20Inversion_JJGu_2012.pdf.
Katsuhiro Tomioka, Masatoshi Yoshimura, "A III-V Nanowire channel on silicon for high-performance vertical transistors", NATURE,
Vol.488, pp-189-193, August 2012, file:///C:/Users/PC53/Downloads/8008_acc.pdf.
C. Thelander, P. Caro, S. Plissard, A. W. Dey, K. A. Dick, “Effects of Crystal Phase Mixing on the Electrical Properties of InAs
Nanowires”, Nano Letters, Vol.11, published date-29 th April-2011, pp-2424-2429, A.C.S. publication,
https://pubs.acs.org/doi/10.1021/nl2008339
S. Chopra, S. Subramaniam, S. M. Joshi and R. N. Awale, "Novel gate-all around triangular channel horizontal nanowire field-effect
transistor for low power memories," 2015 International Conference on Information Processing (ICIP), Pune, 16-19 December-2015, pp.
-59, pune, India, IEEE Xplore, https://ieeexplore.ieee.org/document/7489350.
Subha Subramaniam, Sangeeta.M.Joshi, R.N.Awale, “Analytical modeling and numerical simulation of novel double-gate InGaAs vertical
Nanowire transistor device for threshold voltage tuning and improved performance ”,Engineering Science and Technology (JESTCH),
Elsevier Journal, Vol.19, issue-4, pp-1857-1863 ,December 2016, https://www.sciencedirect.com/science/article/pii/S2215098616303512.
DOI: https://doi.org/10.37591/jovdtt.v13i2.7436
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